Loading......

  How IT ALL STARTED
  PREFACE
1 The Method of Logical Effort
  1.1  Introduction  2
  1.2  Delay in a Logic Gate  5
  1.3  Multistage Logic Networks 13
  1.4  Choosing the Best Number of Stages  20
  1.5  Summary of the Method  22
  1.6  A Look Ahead  24
  1.7  Exercises  25
2  Design Examples
  2.1  The AND Function of Eight Inputs  28
  2.2  Decoder  32
  2.3  Synchronous Arbitration  35
  2.4  Summary  43
  2.5  Exercises 44
3 Deriving the Method of Logical Effort
  3.1  Model of a Logic Gate  46
  3.2  Delay in a Logic Gate  48
  3.3  Minimizing Delay along a Path  51
  3.4  Choosing the Length of a Path  53
  3.5  Using the Wrong Number of Stages  57
  3.6  Using the Wrong Gate Size  59
  3.7  Summary  61
  3.8  Exercises  61
4 Calculating the Logical Effort of Gates
  4.1  Definitions of Logical Effort  64
  4.2  Grouping Input Signals  65
  4.3  Calculating Logical Effort  66
  4.4  Asymmetric Logic Gates  69
  4.5  Catalog of Logic Gates  71
  4.6  Estimating Parasitic Delay  80
  4.7  Properties of Logical Effort  82
  4.8  Exercises  83
5 Calibrating the Model
  5.1  Calibration Technique  87
  5.2  Designing Test Circuits  90
  5.3  Other Characterization Methods  98
  5.4  Calibrating Special Circuit Families  101
  5.5  Summary  102
  5.6  Exercises  102
6 Asymmetric Logic Gates
  6.1  Designing Asymmetric Logic Gates  105
  6.2  Applications of Asymmetric Logic Gates  109
  6.3  Summary  113
  6.4  Exercises  113
7 Unequal Rising and Falling Delays
  7.1  Analyzing Delays  116
  7.2  Case Analysis  120
  7.3  Optimizing CMOS P/N Ratios  125
  7.4  Summary  127
  7.5  Exercises  128
8 Circuit Families
  8.1  Pseudo-NMOS Circuits  130
  8.2  Domino Circuits  133
  8.3  Transmission Gates  146
  8.4  Summary  148
  8.5  Exercises  149
9 Forks of Amplifiers
  9.1  The Fork Circuit Form  152
  9.2  How Many Stages Should a Fork Use?  155
  9.3  Summary  160
  9.4  Exercises  161
10 Branches and Interconnect
  10.1  Circuits That Branch at a Single Input  164
  10.2 Branches after Logic  170
  10.3 Circuits That Branch and Recombine  172
  10.4 Interconnect  175
  10.5 A Design Approach  177
  10.6 Exercises  179
11 Wide Structures
  11.1 An n-input AND Structure  181
  11.2 An n-input Muller C-element  186
  11.3 Decoders  191
  11.4 Multiplexers  196
  11.5 Summary  202
  11.6 Exercises  203
12 Conclusions
  12.1 The Theory of Logical Effort  205
  12.2 Insights from Logical Effort  208
  12.3 A Design Procedure  210
  12.4 Other Approaches to Path Design  213
  12.5 Shortcomings of Logical Effort  215
  12.6 Parting Words  216
APPENDICES
A Cast of Characters
B Reference Process Parameters
C Solutions to Selected Exercises
BIBLIOGRAPHY
INDEX